AMD K10
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AMD K10是下一世代AMD處理器使用的微架構，早前曾有媒體報導K10為已取消的計劃，其後AMD發言人否認此說法，宣佈K10將是AMD K8產品（Athlon 64、Opteron、Sempron 64等）的後繼者。
[编辑] 命名最初AMD K10被认为叫做K8L。 这个"K8L"最早来自Charlie Demerjian在The Inquirer上发布的一篇传闻[1]上面提到K10遭到取消，AMD将改为发布K8L。 [编辑] 历史资料In 2003, AMD outlined the features for upcoming generations of microprocessors after K8 family of processors in various events and analyst meetings, including the Microprocessor Forum 2003 [2]), the outlined features to be deployed by the next-generation microprocessors are as follows:
However, as of 2006, some of the original outlined features had been abandoned, examples as the high processor clock speed due to thermal limitations, and some others were not implemented, such as threaded architectures [來源請求] . On April 13, 2006, Henri Richard, AMD executive vice president and chief officer for marketing and sales, acknowledged[3] the existence of the new microarchitecture in an interview. In June 2006, AMD executive vice president Henri Richard had another interview with DigiTimes commented on the upcoming processor developments:
[编辑] 确认时间
On July 21 2006, AMD President and Chief operating officer (COO) Dirk Meyer and Senior VP Marty Seyer confirmed that the launch date of new microprocessors of Revision H under the new microarchitecture is slated for the middle of 2007; and that it will contain a quad core version for servers, workstations, and high-end desktops, as well as a dual core version for consumer Desktops. Some of the Revision H Opterons shipped in 2007 will have a thermal design power of 68 W. 2006年8月15日，AMD在发布了1207接口的皓龙处理器的同时宣布真正四核皓龙处理器的设计已经完成。[5] [编辑] Internal Code NamesAs of November 2006, reports leaked the upcoming desktop part codenames Agena, Agena FX,[6] and the core speeds of the parts range from 2.4 GHz - 2.9 GHz respectively, 512 KiB L2 cache each core, 2 MiB L3 cache, using HyperTransport 3.0, with a TDP of 125 W.[7] In recent reports, single core variants (codenamed Spica) and dual core with or without L3 cache (codenamed Kuma and Rana respectively) are available.[8] variants under the same microarchitecture [9]. During the AMD Analyst Day 2006 on December 14, 2006, AMD announced their official timeline for server, desktop and mobile processors.[10] For the servers segment, AMD will unveil two new processors based on the architecture codenamed "Barcelona" and "Budapest" for more than 1-way and 1-way servers respectively [10]. Desktops will see an overhaul of the entire processor lineup. Single-core "Lima" built on 65 nm fabrication process node the single-core processors will arrive in Q1 2007 while Sparta, the Sempron 65 nm process update, will come in Q2 2007. For the second half of 2007, HyperTransport 3.0 and Socket AM2+ will be unveiled, which are designed for the specific implementation of the aforementioned consumer quad core desktop chip series, with naming convention changes from city names (up to middle of 2007) to stars or constellations after that, such as Agena; in addition, the AMD Quad FX platform and its immediate successor will support the high end enthusiast dual-processor versions of the chip, codenamed as Agena FX [11], updates the procesors line for AMD Quad FX platform. As with the server chips codenamed Barcelona, the new desktop quad core series will feature a shared L3 cache, 128-bit floating point (FP) units and an enhanced microarchitecture. Agena, the native quad-core processor for the desktop. Kuma, a dual-core variant will follow on in Q3 while Rana, the dual-core version with no shared L3 cache is expected at the end of the year [12]. [编辑] Reported Initial Launch ModelsProcessor models at launch have been reported as follows [13]. According to the most recent report, the mid-range and high-end K10 desktop microprocessors will no longer use the trademark "Athlon", but will don the new name: "Phenom".[14] The low-end (Rana) processors without L3 cache will continue to use the Athlon 64 X2 moniker.[15]
It is worth to note that the number used to classify each processors have changed from PR ratings to other naming conventions like working clock frequencies and other numbers to differentiate performance of different processors as in Intel Core 2 Duo processors naming number conventions. [编辑] Subsequent Product LaunchesWith reports in early April suggesting some upcoming models having a smaller TDP at 45 W [16], and more information about the upcoming chip codenamed "Montreal" [17] using MCM technique of two "Shanghai" cores with a total of 12 MiB L3-cache [18] codenamed AMD K10.5 [19]. [编辑] Live demonstrationsOn November 30, 2006, AMD live demoed the native quad core chip known as "Barcelona" for the first time in public,[20] while running Windows Server 2003 64-bit Edition. AMD claims 70% scaling of performance in real world loads, and better performance than Intel Xeon 5355 processor codenamed Clovertown [21]. More details regarding this first revision of the next generation AMD microprocessor design have surfaced on the web recently including their clock speeds.[22][23] On January 24, 2007, AMD Executive Vice President Randy Allen claimed that in live tests, in regard to a wide variety of workloads, "Barcelona" was able to demonstrate 40% performance advantage over the comparable Intel Xeon codenamed Clovertown dual-processor (2P) quad-core processors [24]. The expected performance of floating point per core would be approximately 1.8 times that of the K8 family, at the same clock speed [25]. [编辑] Sister microarchitectureAlso due in a similar timeframe will be a sister microarchitecture, which will focus on lower power consumption chips in mobile platforms as well as small form factor features. This microarchitecture will contain specialized features such as mobile optimized crossbar switch and memory controller and other on-die components; link power management for HyperTransport 3.0; and others. At that time, AMD simply dubbed it "New Mobile Core", without giving a specific codename. On the December 2006 analyst day, Executive vice president Marty Seyer announced the new mobile core codenamed Griffin to be launched in 2008 [26]. [编辑] Iterations of the releaseIn late 2007 to second quarter of 2008, there will be a modification to the core to be fabricated at 45 nm process node [27], with enhancements such as FB-DIMM support, Direct Connect Architecture 2.0, enhanced Reliability, Availability and Serviceability (RAS), and probably more for the processor die. The platform will also add support for I/O Virtualization, PCI Express 2.0, 10 Gigabit NIC, larger caches, and more. However, reports have suggested that FB-DIMM support had been dropped from future roadmaps of the majority of AMD products since popularity is low [28][29]. Also, FB-DIMM's future as an industry standard had been called into question. A recent article published by The Inquirer corroborates the earlier reports of the timeline (as cited in this article). According to the report, there will be three iterations of the core: one named Barcelona, due in Q2 of 2007, with new CPU core components as well as the microarchitecture, but built on the old HyperTransport 2.0 infrastructure; the second is Budapest for single socket systems using socket AM2+ or socket AM3, with HyperTransport 3.0; and the third, codenamed Shanghai is an update of the server chip, based on 45 nm process [30], probably also with HyperTransport 3.0 and DDR3 implementation, due in Q1-Q2 2008.[31] In 2008, AMD will introduce Deneb FX for the replacement for the AMD Quad FX platform, as well as Deneb for the mainstream. Propos and Regor will also replace Kuma and Rana in the lower market segments. Socket AM2+ being named in the late 2006 might actually have been the original AM3 socket, but as naming conventions changed, so that the next generation of consumer desktop socket capable of DDR3 will be socket AM3. [32] [编辑] Features[编辑] Fabrication technology
AMD will introduce the microprocessors manufactured at 65 nm feature width using Silicon-on-insulator (SOI) technology, since the release of K10 coincides with the volume ramp of this manufacturing process [33]. The servers will be produced for Socket F or Socket F+ (1207) infrastructure, the only server socket on AMD's near-term roadmap; the desktop parts will come on Socket AM2 or Socket AM2+. AMD announced during the Technology Analyst Day [34] that the use of Continuous Transistor Improvement (CTI) and Shared Transistor Technology (STT) would finally lead to the implementation of Silicon-Germanium-On-Insulator (SGoI) on 65 nm process CPUs [35]. [编辑] Supported DRAM standardsThe K8 family was known to be particularly sensitive to memory latency since its design gains performance by minimizing this through the use of an on-die memory controller (integrated into the CPU); increased latency in the external modules negates the usefulness of the feature. DDR2 RAM introduces some additional latency over traditional DDR RAM since the DRAM is internally driven by a clock at one quarter of the external data frequency, as opposed to one half that of DDR. However, since the command clock rate in DDR2 is doubled relative to DDR and other latency-reducing features (e.g. additive latency) have been introduced, common comparisons based on CAS Latency alone are not sufficient. For example, Socket AM2 processors are known to demonstrate similar performance using DDR2 SDRAM as Socket 939 processors that utilize DDR-400 SDRAM. K10 processors supports DDR2 SDRAM rated up to DDR2-1066 (1066 MHz) [36]. [编辑] Higher computational throughputIt was also reported by several sources (such as AnandTech, The Inquirer and Geek.com) that the microprocessors implementing the microarchitecture will feature a doubling in the width of SSE execution units in the cores. With the help of major improvements in the memory subsystem (such as load re-ordering and improved prefetch mechanisms) as well as the doubled instruction fetch and load, it is expected to increase the suitability of the processor to scientific and high-performance computing tasks and potentially improve its competitiveness with Intel's Xeon, Core 2, Itanium 2 and other contemporary microprocessors. Many of the improvements in computational throughput of each core are listed below. [编辑] Characteristics of the microarchitecture
[编辑] 下一代Codenamed "Fusion" is a CPU technology furthering the trend of continued system component integration onto CPU die (which was initiated by K8 with integrated SRQ, cross-bar switch, memory controller as well as Hypertransport links), planned beyond these two afore mentioned families of products, and will be due in late 2008 or sometime in 2009. It is not clear what additional codenames will be given to these. [编辑] 媒体讨论Note: These media discussions are sorted by dates of publishing in ascending orders.
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[编辑] 外部连接
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